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Částečná dynamická rekonfigurace na FPGA obvodech firmy Xilinx s nástroji ISE a EDK verze 8.2i
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SYSNO ASEP 0081217 Document Type E - Electronic Document R&D Document Type R&D Presentation (audio-visual, electronic documents. Documents released only in a form readable by a computer (eg . documents released on CD only), available only via the Internet, WEB presentation. Title Částečná dynamická rekonfigurace na FPGA obvodech firmy Xilinx s nástroji ISE a EDK verze 8.2i Title Partial Dynamic Reconfiguration in Xilinx FPGA Circuits with ISE 8.2i and EDK 8.2i tools Author(s) Kohout, Lukáš (UTIA-B) RID Issue data Praha: ÚTIA AV ČR, 2007 Publication form CD ROM - CD ROM Language cze - Czech Country CZ - Czech Republic Keywords FPGA ; dynamic reconfiguration Subject RIV JC - Computer Hardware ; Software R&D Projects 1M0567 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ AV0Z10750506 - UTIA-B (2005-2011) Annotation Obsahem tohoto dokumentu je popis aplikace využívající částečné dynamické rekonfigurace na FPGA obvodech firmy Xilinx. Implementován je FIR filtr na ML402 desce firmy Xilinx. Použitými nástroji jsou ISE a EDK ve verzi 8.2i. Description in English This application note describes the use of the partial dynamic reconfiguration in Xilinx FPGA circuits. The FIR filter is implemented in Xilinx ML402 evaluation platform. Used tools are ISE and EDK in 8.2i version. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201. Year of Publishing 2007
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