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Lattice for FPGAs using logarithmic arithmetic
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SYSNO ASEP 0410837 Document Type J - Journal Article R&D Document Type Journal Article Subsidiary J Ostatní články Title Lattice for FPGAs using logarithmic arithmetic Author(s) Kadlec, Jiří (UTIA-B) RID
Matoušek, Rudolf (UTIA-B)
Heřmánek, Antonín (UTIA-B)
Líčko, Miroslav (UTIA-B)
Tichý, Milan (UTIA-B)Source Title Electronic Engineering - ISSN 0013-4902
Roč. 74, č. 906 (2002), s. 53-56Number of pages 4 s. Language eng - English Country GB - United Kingdom Keywords lattice Rls algorithm ; FPGA ; logarithmic arithmetic Subject RIV JC - Computer Hardware ; Software CEZ AV0Z1075907 - UTIA-B Annotation Presented here are implementations of a complete RLS Lattice cores for Virtex. Their computational parallelism and ease of pipelining lead to easy mapping on FPGA. Internally, the computations are based on 32bit or 20bit logarithmic arithmetic (LNS). Compared are the 32bit LNS-SINGLE-ALU and 20bit LNS-QUAD-ALU versions. On Virtex XCV2000E-6, these use 27%, 54% or 40% of slices respectively and run at 50, 35 and 42 MHz on the Celoxica RC1000 board. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
Number of the records: 1