Dynamic runtime partial reconfiguration in FPGA

0411119 - UTIA-B 20030106 RIV CZ eng C - Conference Paper (international conference)
Matoušek, Rudolf - Daněk, Martin - Pohl, Zdeněk - Kadlec, Jiří
Dynamic runtime partial reconfiguration in FPGA.
Liberec: Technical University, 2003. ISBN 80-7083-708-X. In: ECMS 2003. 6th International Workshop on Electronics, Control, Measurement and Signals. - (Nouza, J.; Drábková, J.), s. 294-298
[ECMS 2003 /6./. Liberec (CZ), 02.06.2003-04.06.2003]
Grant - others:EU IST(XE) IST-2001-34016
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * runtine dynamic reconfiguration * VHDL
Subject RIV: JC - Computer Hardware ; Software

Runtime dynamic reconfiguration of FPGA devices has been an issue of the last decade. Although this feature permits more robust and more flexible designes and devices that posseses it are available on the market, it is not directly supported by the current design tools. This paper presents a simple design that uses true dymnamic reconfiguration for Atmel AT94K devices. The design has been implemented using a special feature of the currently available Figaro IDS5.2 tool in an innovative way.
Permanent Link: http://hdl.handle.net/11104/0131206