Number of the records: 1
A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic
- 1.
SYSNO ASEP 0410735 Document Type V - Research Report R&D Document Type The record was not marked in the RIV Title A Comparison of FPGA Implementation of the A Priori Error-Feedback LSL Algorithm using Logarithmic Arithmetic Author(s) Albu, F. (IE)
Kadlec, Jiří (UTIA-B) RID
Matoušek, Rudolf (UTIA-B)
Heřmánek, Antonín (UTIA-B)
Coleman, J. N. (GB)Issue data Praha: ÚTIA AV ČR, 2001 Series Research Report Series number 2035 Number of pages 5 s. Language eng - English Country CZ - Czech Republic Keywords LSL Algorithm ; FPGA ; digital signal processing Subject RIV JC - Computer Hardware ; Software R&D Projects LN00B096 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ 1075907 Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
Number of the records: 1