Modeling the influence of vias on signal integrity
1.
SYSNO ASEP
0304073
Document Type
C - Proceedings Paper (int. conf.)
R&D Document Type
Conference Paper
R&D Document Type
W - Uspořádání workshopu
Title
Modeling the influence of vias on signal integrity
Author(s)
Žilka, Zdeněk (URE-Y) Berka, Zbyněk (URE-Y) Braun, Jaromír (URE-Y)
Issue data
Brno: Vysoké učení technické, 2002
ISBN
80-214-2180-0
Source Title
EDS'02 Proceedings of 9th Electronic Devices and Systems Conference 2002 and Experimental Methods in Acoustic and Electromagnetic Emission International Workshop 2002 / Musil V.
Pages
s. 284-287
Number of pages
4 s.
Action
Electronic Devices and Systems Conference EDS' /9./
Event type
W - Workshop
Event date
09.09.2002-10.09.2002
VEvent location
Brno
Country
CZ - Czech Republic
Event type
EUR
Language
eng - English
Country
CZ - Czech Republic
Keywords
signal processing ; analogue simulation
Subject RIV
JA - Electronics ; Optoelectronics, Electrical Engineering
R&D Projects
KSK1019101 Projekt 01/01:4013 GA AV ČR - Academy of Sciences of the Czech Republic (AV ČR)
CEZ
AV0Z2067918 - URE-Y
Annotation
The influence of vias on signal integrity in mixed-signal systems manufactured as multi-layer printed circuit boards is investigated. The simpler models and guidelines are introduced, which are intended for the designer to help him in creating virtual prototype computer model of the system.
