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Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW
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SYSNO ASEP 0410165 Document Type K - Proceedings Paper (Czech conf.) R&D Document Type The record was not marked in the RIV Title Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW Author(s) Kadlec, Jiří (UTIA-B) RID
Matoušek, Rudolf (UTIA-B)
Vialatte, Christian (UTIA-B)
Coleman, J. N. (GB)Issue data Praha: VŠCHT, 1999 ISBN 80-7080-354-1 Source Title Sborník příspěvků 7. ročníku konference MATLAB '99
s. 84-90Number of pages 7 s. Action MATLAB '99 /7./ Event date 03.11.1999 VEvent location Praha Country CZ - Czech Republic Language eng - English Country CZ - Czech Republic CEZ 1075907 Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
Number of the records: 1