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RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic
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SYSNO 0410739 Title RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic Author(s) Kadlec, Jiří (UTIA-B) RID
Albu, F. (IE)
Softley, Ch. (GB)
Matoušek, Rudolf (UTIA-B)
Heřmánek, Antonín (UTIA-B)Issue data Praha: ÚTIA AV ČR, 2001 Edition Research Report , 2036 Document Type Výzkumná zpráva Grant HSLA 33544, XE - EU countries LN00B096 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ 1075907 Language eng Country CZ Keywords digital signal processing * logaritmic arithmetic * embedded compilation Permanent Link http://hdl.handle.net/11104/0130827
Number of the records: 1