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RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic
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SYSNO ASEP 0410739 Document Type V - Research Report R&D Document Type The record was not marked in the RIV Title RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic Author(s) Kadlec, Jiří (UTIA-B) RID
Albu, F. (IE)
Softley, Ch. (GB)
Matoušek, Rudolf (UTIA-B)
Heřmánek, Antonín (UTIA-B)Issue data Praha: ÚTIA AV ČR, 2001 Series Research Report Series number 2036 Number of pages 11 s. Language eng - English Country CZ - Czech Republic Keywords digital signal processing ; logaritmic arithmetic ; embedded compilation Subject RIV JC - Computer Hardware ; Software R&D Projects LN00B096 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) CEZ 1075907 Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
Number of the records: 1