Number of the records: 1  

RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic

  1. 1.
    Kadlec, Jiří - Albu, F. - Softley, Ch. - Matoušek, Rudolf - Heřmánek, Antonín
    RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic.
    Praha: ÚTIA AV ČR, 2001. 11 s. Research Report, 2036.
    http://hdl.handle.net/11104/0130827

Number of the records: 1  

  This site uses cookies to make them easier to browse. Learn more about how we use cookies.