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RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic
- 1.Kadlec, J., Albu, F., Softley, C., Matoušek, R., Heřmánek, A. RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic. Praha: ÚTIA AV ČR, 2001. Research Report, 2036.
Number of the records: 1