Number of the records: 1  

RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic

  1. 1.
    Kadlec, J., Albu, F., Softley, C., Matoušek, R., Heřmánek, A. RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic. Praha: ÚTIA AV ČR, 2001. Research Report, 2036.

Number of the records: 1  

  This site uses cookies to make them easier to browse. Learn more about how we use cookies.