Number of the records: 1

Reliable FPGA Architecture

SYSNO	0524715
Title	Reliable FPGA Architecture
Author(s)	Pospíšil, Jan (UJF-V) [OJS]
Issue data	Praha: České vysoké učení technické, 2018
Academic degree	Ph.D.
Place of presentation and defence	České vysoké učení technické v Praze, Fakulta informačních technologií
Affiliation	Ústav jaderné fyziky AV ČR, v. v. i.
Document Type	Dizertace
Grant	LM2015056 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
	LM2015058 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
Institutional support	UJF-V - RVO:61389005
Language	eng
Country	CZ
Keywords	FPGA * single event upset * simulation * fault model * XDL * RapidSmith
Cooperating institutions	České vysoké učení technické v Praze, Fakulta informačních technologií (Czech Republic)
URL	http://hdl.handle.net/10467/82108
Permanent Link	http://hdl.handle.net/11104/0309023

Number of the records: 1