FPGA ; single event upset ; simulation ; fault model ; XDL ; RapidSmith
Subject RIV
IN - Informatics, Computer Science
OECD category
Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
R&D Projects
LM2015056 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
LM2015058 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
Institutional support
UJF-V - RVO:61389005
Annotation
Different types of Field Programmable Gate Arrays (FPGA) are used in many different fields of electronics. The most prevalent type is SRAM-based, which uses static RAM cells to store its configuration. The inherent drawback of this technology is its susceptibility to Single Event Effects. The Single Event Upset is the main concern, which can result not only in corrupted data being processed, but also in a major change to the design function and connections. Mitigation techniques are known to handle this issue, but their impact evaluation is not always easy. The actual impact to the reliability of a given design needs to be evaluated taking into account not only changes made to the design on the RegisterTransfer Level, but also the actual implementation of the design on a given FPGA. In our work, the main focus is on the FPGA architecture and its reliability in terms of radiation induced soft errors. We provide an overview of all the background needed to successfully handle this issue in this thesis. Later, an overview of the related works dealing with the similar topics and also connected research are presented. The method for a simulation-based evaluation of radiation induced soft errors in the SRAM-based FPGA configuration memory is proposed, an example implementation of this method on a chosen FPGA family is described, and individual steps are explained. Results of this example implementation on a set of benchmarks are presented and discussed.
