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Pipelined logarithmic 32bit ALU for Celoxica DK1
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SYSNO ASEP 0410671 Document Type K - Proceedings Paper (Czech conf.) R&D Document Type The record was not marked in the RIV Title Pipelined logarithmic 32bit ALU for Celoxica DK1 Author(s) Heřmánek, Antonín (UTIA-B)
Kadlec, Jiří (UTIA-B) RID
Matoušek, Rudolf (UTIA-B)
Líčko, Miroslav (UTIA-B)
Pohl, Zdeněk (UTIA-B) RIDIssue data Praha: VŠCHT, 2001 ISBN 80-7080-446-7 Source Title Sborník příspěvků 9.ročníku konference MATLAB 2001 / Procházka A. ; Uhlíř J.
s. 72-80Number of pages 9 s. Action MATLAB 2001 /9./ Event date 11.10.2001 VEvent location Praha Country CZ - Czech Republic Event type CST Language eng - English Country CZ - Czech Republic Subject RIV JC - Computer Hardware ; Software CEZ 1075907 Annotation This paper presents and compares two possible solution for floating point-like HW, based on a 32bit logarithmic ALU. There are described the implementation, parametres nad the basic use of a non-pipelined ALU. Both Virtex FPGA cores are encapsulated in function like API interface compatible with Handel-C 2.1 and the new DK1 tool from Celoxica. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
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