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UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

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    SYSNO ASEP0380863
    Document TypeB - Monograph
    R&D Document TypeMonograph
    TitleUTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
    Author(s) Daněk, Martin (UTIA-B)
    Kafka, Leoš (UTIA-B)
    Kohout, Lukáš (UTIA-B) RID
    Sýkora, Jaroslav (UTIA-B)
    Bartosinski, Roman (UTIA-B)
    Number of authors5
    Issue dataNew York: Springer, 2013
    ISBN978-1-4614-2409-3
    SeriesCircuits & Systems
    Number of pages209 s.
    Publication formPrint - P
    Languageeng - English
    CountryUS - United States
    Keywordsmulti-threading ; micro-threading ; SPARC ; LEON3 ; hardware acceleration ; FPGA ; GRLIB
    Subject RIVJC - Computer Hardware ; Software
    R&D Projects7E08013 GA MŠMT - Ministry of Education, Youth and Sports (MEYS)
    DOI https://doi.org/10.1007/978-1-4614-2410-9
    AnnotationThis book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. * Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; * Provides VHDL sources for the described processor; * Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; * Includes programming by example in the micro-threaded assembly language.
    WorkplaceInstitute of Information Theory and Automation
    ContactMarkéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201.
    Year of Publishing2013
Number of the records: 1  

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