Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
1.
SYSNO ASEP
0306846
Document Type
C - Proceedings Paper (int. conf.)
R&D Document Type
Conference Paper
Title
Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs
Title
Analýza možností použití částečné dynamické rekonfigurace v emulátoru poruch v FPGA Xilinx
Author(s)
Kafka, Leoš (UTIA-B)
Source Title
Proceedings 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. - Piscataway : IEEE, 2008 / Straube Bernd ; Drutarovský Miloš ; Renovell Michel ; Gramata Peter ; Fischerová Mária
- ISBN 978-1-4244-2276-0
Pages
s. 178-181
Number of pages
4 s.
Action
IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. DDECS 2008 /11./
1QS108040510 GA AV ČR - Academy of Sciences of the Czech Republic (AV ČR)
CEZ
AV0Z10750506 - UTIA-B (2005-2011)
Annotation
This paper analyses applicability of partial runtime reconfiguration (PRR) in fault emulators based on FPGAs of Xilinx Virtex family. PRR is used for loading emulator modules and for injecting faults into the emulated circuit. Since the time of reconfiguration may have significant impact on its usability, this paper deals with this issue. The goal was to accelerate PRR and to evaluate the time needed for fault injection by PRR on these FPGAs. Experimental results show that we have achieved up to eight times faster reconfiguration compared to the original Xilinx method, and fault injection time about 77us per one emulated fault.
