Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board

0461500 - ÚTIA 2017 RIV CZ eng L - Prototype, f. module
Kadlec, Jiří - Pohl, Zdeněk - Kohout, Lukáš
Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board.
Internal code: t20i2h1 ; 2016
Technical parameters: Demonstrátor umožňuje zpracovávat video signál z Full HD HDMI vstupu v obvodu Zynq ZC7020-2I s výstupem na Full HD HDMI monitor.
Economic parameters: Video signál je zpracováván pomocí HW akcelerátorů. Oproti SW řešení je dosahováno zrychlení 5x až 30x, a to v případě detekce hran v obraze a detekce pohybu v reálném čase s rozlišením 1920x1080p60 s výstupem na Full HD monitor.
R&D Projects: GA MŠMT 7H14004
Keywords : FPGA * Full HD HDMI video processing * Zynq System-on-Module
Subject RIV: JC - Computer Hardware ; Software
http://sp.utia.cz/index.php?ids=results&id=t20i2h1

This application note describes use of an evaluation package with 3 edge detection and 3 motion detection video processing designs on the Trenz TE0701-05 platform with industrial grade Zynq XC7Z020-2I device on System on Module TE0720-03-2I. All demonstrated video processing algorithms have been developed, debugged and tested in Xilinx SDSoC 2015.4 environment. Algorithms have been compiled by Xilinx SDSoC 2015.4 system level compiler (based on the Xilinx HLS compiler) to Vivado 2015.4 projects, and compiled by Vivado 2015.4 to bitstreams. The SW access functions controlling the HW accelerators have been exported to the Xilinx SDK 2015.4 SW projects as static .a libraries for standalone ARM Cortex A9 applications. This application note also describes 4 edge detection algorithms defined in the SDSoC 2015.4 in form, which enables in the SDK 2015.4 the parallel execution of predefined video processing HW paths with C user code on ARM.
Permanent Link: http://hdl.handle.net/11104/0261352