EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board

0451807 - ÚTIA 2016 RIV CZ eng L - Prototype, f. module
Kadlec, Jiří
EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board.
Internal code: Utia_EdkDSP_Vivado_2014_4_AC701 ; 2015
Technical parameters: Demonstrátor umožňuje ověření funkce akcelerátorů výpočtu v plovoucí řádové čárce na ARTIX FPGA na desce AC701 s výkonem až 10 GFLOP/s.
Economic parameters: Ověření funkce akcelerátorů výpočtu v plovoucí řádové čárce na ARTIX FPGA spolu s 1 Gb ethernetem pro aplikace v internetu věcí.
R&D Projects: GA MŠMT 7H14007
Institutional support: RVO:67985556
Keywords : FPGA * floating-point accelerator * ethernet * Internet of Things
Subject RIV: JC - Computer Hardware ; Software
http://sp.utia.cz/index.php?ids=results&id=Utia_EdkDSP_Vivado_2014_4_AC701

This application note describes precompiled Vivado 2014.4 Artix7 designs with the floating point EdkDSP accelerators and examples. The evaluation MicroBlaze SoC design with the AXI-lite bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Artix7 AC701 board and the Vivado 2014.4 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP TCP/IP stack library v1.4.1 with Xilinx adapter v2.2. The implementation follows guidelines described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 5 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable computing data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx AC701 board with the 28nm Artix7 xc7a200t-2 device. This application note explains how to install and use the demonstrator on Windows7, (32 or 64 bit) and the Xilinx AC701 development board.
Permanent Link: http://hdl.handle.net/11104/0253189