Fast Hardware Implementation of NNSU Separating Algorithm

0446430 - ÚI 2016 RIV US eng C - Conference Paper (international conference)
Hakl, František
Fast Hardware Implementation of NNSU Separating Algorithm.
Real Time Conference (RT). Piscataway: IEEE, 2014, s. 1-8. ISBN 978-1-4799-3659-5.
[RT 2014. IEEE-NPSS Real Time Conference /19./. Nara (JP), 23.05.2014-26.05.2014]
R&D Projects: GA MŠMT(CZ) LG12020; GA TA ČR TA01010490
Institutional support: RVO:67985807
Keywords : neural networks * data filtering * fast data processing
Subject RIV: IN - Informatics, Computer Science

This paper has two objectives. First, we introduce a separation algorithm of a neural network with switching units (NNSU), and present its applicability to processing selected MonteCarlo (MC) data channels of the LHC detector in CERN Geneve and selected MC data of DO-detector in FNAL. The result achieved by this algorithm provides better separation of signal and background events than classical cut-based methods and the separation result is comparable to TMVA ROOT methods, such as BDT and MLP. The training phase of NNSU uses a genetic optimization of NNSU architecture, hence a convenient definition of corresponding fitness function allows for refinement of separation results to meet user defined requirements. In the next parts we discuss the possibility of efficient hardware implementation. NNSU algorithm is in fact a piecewise linear discrimination and, therefore, testing phase of the algorithm can be performed by hardware means. First step toward hardware implementation was done, and possibility of full electronic implementation was studied. On the base of this study we estimate that event processing speed about 25 mega-samples per second is reachable by full hardware implementation without significant degradation of separation quality.
Permanent Link: http://hdl.handle.net/11104/0248511