Fault classification for self-checking circuits implemented in FPGA

0411313 - UTIA-B 20050041 RIV HU eng C - Conference Paper (international conference)
Kafka, Leoš - Kubalík, P. - Kubátová, H. - Novák, O.
Fault classification for self-checking circuits implemented in FPGA.
[Klasifikace poruch pro samočinně kontrolované obvody.]
Sopron: University of West Hungary, 2005. ISBN 963-9364-48-7. In: Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronics Circuits and Systems. - (Takách, G.; Hlawiczka, A.; Sziray, J.), s. 228-231
[IEEE Design and Diagnostics of Electronics Circuits and Systems Workshop /8./. Sopron (HU), 13.04.2005-16.04.2005]
R&D Projects: GA ČR GA102/04/2137
Institutional research plan: CEZ:AV0Z10750506
Keywords : concurrent error detection * FPGA * ED codes
Subject RIV: JC - Computer Hardware ; Software

This work supports the design process of CED circuits implemented in FPGAs. We propose a new fault classification. We can summarize that our classification leads to a more accurate evaluation of the fault coverage, and we can determine whether the tested circuit satisfies the FS and ST properties. We can also evaluate how many considered faults violate the FS and ST property.

Článek se zabývá novou klasifikací poruch vhodnou pro samočinně kontrolované obvody. Poruchy jsou rozděleny podle jejich vlivu na bezpečnost proti poruchám a samočinnou kontrolu obvodu, a tak, na rozdíl od běžné klasifikace poruch, umožňuje přesněji vyhodnotit vlastnosti obvodu.
Permanent Link: http://hdl.handle.net/11104/0131396