0411279 - UTIA-B 20050006 RIV CZ cze J - Journal Article
Mazanec, Tomáš - Brothánek, M.
FPGA implementace LMS a N-LMS algoritmu pro potlačení akustického echa.
[The FPGA implementation of LMS and N-LMS of echo canceller.]
Akustické listy. Roč. 10, č. 4 (2004), s. 9-13. ISSN 1212-4702
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA * LMS algorithm * Handel-C
Subject RIV: JC - Computer Hardware ; Software

Cílem práce bylo implementovat metodu kompenzace echa na platformě programovatelného obvodu FPGA. Řešení zahrnuje jak praktické využití adaptivní filtrace, tak implementaci zadané úlohy do HW podoby.

This article describes implementation of echo canceller on a FPGA programmable device (Xilinx, Virtex), which was done. The solution of this adaptive filtering task was aimed to least squares algorithms, especially to the LMS and normalized LMS algorithm. Used digital filterswere the type of finite impulse response in transveral structure. The FPGA implementation was created in Handel-C of DK 2.0 system which is designed to rapis prototyping flow.
Permanent Link: http://hdl.handle.net/11104/0131362