Integrated iterative approach to FPGA placement

0411196 - UTIA-B 20030183 CZ eng K - Conference Paper (Czech conference)
Daněk, Martin
Integrated iterative approach to FPGA placement.
Brno: VUT, 2003. ISBN 80-214-2471-0. In: Počítačové Architektury & Diagnostika PAD 2003. - (Kotásek, Z.; Růžička, R.; Sekanina, L.), s. 43-50
[PAD 2003 Počítačové Architektury & Diagnostika. Zvíkovské Podhradí (CZ), 24.09.2003-26.09.2003]
Grant - others:CTU(CZ) 0210413
Institutional research plan: CEZ:AV0Z1075907
Keywords : FPGA placement * global routing * integrated approach
Subject RIV: JC - Computer Hardware ; Software

This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use an unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders.
Permanent Link: http://hdl.handle.net/11104/0131282