Logarithmic arithmetic core based RLS LATTICE implementation

0410794 - UTIA-B 20020008 RIV US eng C - Conference Paper (international conference)
Matoušek, R. - Pohl, Z. - Kadlec, Jiří - Tichý, Milan - Heřmánek, Antonín
Logarithmic arithmetic core based RLS LATTICE implementation.
Los Alamitos: IEEE, 2002. ISBN 0-7695-1471-5. In: Design, Automation and Test in Europe DATE 02. - (Sciuto, D.; Kloos, C.), s. 271
[Design, Automation and Test in Europe DATE 02. Paris (FR), 04.03.2002-08.03.2002]
R&D Projects: GA MŠMT LN00B096
Institutional research plan: CEZ:AV0Z1075907
Keywords : logaritmic arithmetic core * FPGA * LNS
Subject RIV: JC - Computer Hardware ; Software

Presentation of HW implementation of a complete Recursive Least Square (RLS) LATTICE core for Virtex XCV800 device. The computational parallelism and ease of pipelining of LATTICE leads to easy mapping on FPGA. Demonstration of the active noise cancellation with four 20-bit parallel Logarithic Arithemtic ALUs on the XESS HW with Virtex XCV800-4.
Permanent Link: http://hdl.handle.net/11104/0130881