Number of the records: 1
Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW
- 1.0410165 - UTIA-B 990149 CZ eng K - Conference Paper (Czech conference)
Kadlec, Jiří - Matoušek, Rudolf - Vialatte, Christian - Coleman, J. N.
Port of Pascal FPGA-logarithmic-unit simulator to Simulink/RTW.
Praha: VŠCHT, 1999. ISBN 80-7080-354-1. In: Sborník příspěvků 7. ročníku konference MATLAB '99., s. 84-90
[MATLAB '99 /7./. Praha (CZ), 03.11.1999]
Grant - others:MŠMT(CZ) OK 314; MŠMT(CZ) OK 317; Commission EC(XE) ESPRIT 23544 HSLA
Program: OK; OK
Institutional research plan: AV0Z1075907
Permanent Link: http://hdl.handle.net/11104/0130257
Number of the records: 1