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The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator
- 1.0363078 - ÚTIA 2012 RIV CZ eng C - Conference Paper (international conference)
Bartosinski, Roman
The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator.
ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing. Praha: IEEE, 2011, s. 1657-1660. ISBN 978-1-4577-0539-7.
[ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing. Praha (CZ), 22.05.2011-27.05.2011]
R&D Projects: GA MŠMT(CZ) 7H10001
Grant - others:GA MŠk(CZ) JU100230 Artemis
Institutional research plan: CEZ:AV0Z10750506
Keywords : LDU decomposition * directional forgetting * hardware accelerator
Subject RIV: IN - Informatics, Computer Science
http://library.utia.cas.cz/separaty/2011/ZS/bartosinski-0363078.pdf
The paper discusses an RLS algorithm based on the LDU decomposition (LD-RLS) with directional forgetting implemented on an embedded system with a vector-oriented hardware accelerator. The LD-RLS algorithm can be attractive for control applications to identify an unknown system or to track time-varying parameters. A solution of the LD-RLS algorithm directly contains the estimated parameters. It also offers a possibility to use a priori information about the identified system and its parameters. The implementation of the LD-RLS algorithm is done on an FPGA-based accelerator from a high-level abstraction. It is compared with an implementation of the same algorithm in software on the same platform.
Permanent Link: http://hdl.handle.net/11104/0199178
Number of the records: 1