Reed Solomonův kodér a dekodér pro FPGA

0079768 - ÚTIA 2007 RIV CZ cze E - Electronic Document
Heřmánek, Antonín - Dušek, J.
Reed Solomonův kodér a dekodér pro FPGA.
[Reed Solomon coder and decoder for FPGA.]
[program]. - Praha: ÚTIA AV ČR, 2007, 12,8 MB
R&D Projects: GA AV ČR 1ET100750408
Institutional research plan: CEZ:AV0Z10750506
Keywords : FPGA * RS coder * Handel C
Subject RIV: JC - Computer Hardware ; Software

Tento dokument popisuje základní vlastnosti a parametry IP maker pro implementaci Reed Solomonova (RS) kodéru a dekodéru, které byly imlementovány v jazyce Handel-C na obvodech ALTERA Cyclon EP1C12Q240C8 a odzkoušeny na vývojové desce UP2 a UP3-1C12.

This document presents the parameters and demo application for the Reed Solomon coder and decoder IP macros for the Altera FPGA. The coder and two variants of decoder (serial and parallel versions) are presented. Both, coder and decoder, has been implemented on Altera Cyclon EP1C12Q240C8 device and tested on UP3 evaluation board.
Permanent Link: http://hdl.handle.net/11104/0144339