FPGA-based fault simulator

0040206 - ÚTIA 2007 RIV CZ eng C - Conference Paper (international conference)
Kafka, Leoš - Novák, O.
FPGA-based fault simulator.
[Simulátor chyb založený na programovatelném logickém obvodu.]
Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits adn Systems. Prague: Czech Technical University, 2006 - (Reorda, M.; Novák, O.; Straube, B.), s. 274-278. ISBN 1-4244-0184-4.
[DDECS 2006. IEEE Design and Diagnostics of Electronic Circuits and Systems. Prague (CZ), 18.04.2006-21.04.2006]
R&D Projects: GA AV ČR 1QS108040510
Institutional research plan: CEZ:AV0Z10750506
Keywords : falut simulation * FPGA * reconfiguartion
Subject RIV: JC - Computer Hardware ; Software

This paper describes a simulator based an this technique and show that partial dynamic reconfiguration is an effective way of falut injection. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported.

Článek presentuje simulátor chyb založený na programovatelném logickém poli.
Permanent Link: http://hdl.handle.net/11104/0134006