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0410739 - UTIA-B 20010208 CZ eng V - Research Report
Kadlec, Jiří - Albu, F. - Softley, Ch. - Matoušek, Rudolf - Heřmánek, Antonín
RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic.
Praha: ÚTIA AV ČR, 2001. 11 s. Research Report, 2036.
R&D Projects: GA MŠMT LN00B096
Grant - others:ESPRIT(XE) HSLA 33544
Institutional research plan: AV0Z1075907
Keywords : digital signal processing * logaritmic arithmetic * embedded compilation
Subject RIV: JC - Computer Hardware ; Software
Permanent Link: http://hdl.handle.net/11104/0130827