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  1. 1.def.record 'I2_TF_SHORT' not found in 'CavUnTablesd'
  2. 2.def.record 'I2_TF_SHORT' not found in 'CavUnTablesd'
  3. 3.
    0533982 - MÚA 2021 CZ cze V - Research Report
    Bahenská, Marie
    Josef Kurz. Inventář osobního fondu.
    [Josef Kurz. Personal papers inventory.]
    Praha: Masarykův ústav a Archiv AV ČR, 2013. 53 s. Archivní pomůcky, 582.
    Institutional support: RVO:67985921
    Keywords : Josef Kurz * personal papers
    OECD category: History (history of science and technology to be 6.3, history of specific sciences to be under the respective headings)
    Permanent Link: http://hdl.handle.net/11104/0312206
     
  4. 4.def.record 'I2_TF_SHORT' not found in 'CavUnTablesd'
  5. 5.def.record 'I2_TF_SHORT' not found in 'CavUnTablesd'
  6. 6.def.record 'I2_TF_SHORT' not found in 'CavUnTablesd'
  7. 7.
    0346745 - ÚTIA 2011 RIV US eng C - Conference Paper (international conference)
    Heřmánek, Antonín - Kuneš, Michal - Tichý, Milan
    Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.
    Proceedings of the International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2010, s. 336-339. ISBN 978-0-7695-4179-2.
    [20th International Conference on Field Programmable Logic and Applications. Milano (IT), 31.08.2010-02.09.2010]
    R&D Projects: GA MŠMT 7H09005
    Institutional research plan: CEZ:AV0Z10750506
    Keywords : FPGA * Clock Gating * Digital design * System on Chip * Multicore Embedded System * Power consumption
    Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering
    Result website:
    http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf
    Permanent Link: http://hdl.handle.net/11104/0187684
     

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