Reconfigurable Hardware Objects for Image Processing on FPGAs
1.
SYSNO ASEP
0342301
Druh ASEP
C - Konferenční příspěvek (mezinárodní konf.)
Zařazení RIV
D - Článek ve sborníku
Název
Reconfigurable Hardware Objects for Image Processing on FPGAs
Tvůrce(i)
Kloub, Jan (UTIA-B) Honzík, Petr (UTIA-B) Daněk, Martin (UTIA-B)
Zdroj.dok.
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. - Vienna : Institute of Electrical and Electronics Engineers, 2010
- ISBN 978-1-4244-6610-8
Rozsah stran
s. 121-122
Poč.str.
2 s.
Forma vydání
www - www
Akce
Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
7H09005 GA MŠMT - Ministerstvo školství, mládeže a tělovýchovy
CEZ
AV0Z10750506 - UTIA-B (2005-2011)
Anotace
Embedded systems are getting more complex; that is why the high level of abstraction is required during the development process. High abstraction methods simplify implementation of complex computation systems and shorten the time to market. This paper presents an implementation of a graphic computing element (GCE) which can be used as a runtime parametrized building block in image processing applications in FPGAs. In terms of the object oriented model GCE encapsulates its internal data representation and rules for their manipulation. Several basic image processing operations have been implemented (Sobel edge detection, Gauss, mean, etc. filtering). These operations are called as GCE methods. Because of high spatial dependency of image data in image processing, an efficient image data reuse method has been implemented.
