Počet záznamů: 1
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
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$a Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique 215 $a 4 s. 463 -1
$1 001 cav_un_epca*0347026 $1 010 $a 978-0-7695-4179-2 $1 200 1 $a Proceedings of the International Conference on Field Programmable Logic and Applications $v S. 336-339 $1 210 $a Piscataway $c IEEE $d 2010 610 0-
$a FPGA 610 0-
$a Clock Gating 610 0-
$a Digital design 610 0-
$a System on Chip 610 0-
$a Multicore Embedded System 610 0-
$a Power consumption 700 -1
$3 cav_un_auth*0101105 $a Heřmánek $b Antonín $i Zpracování signálů $j Department of Signal Processing $k ZS $l ZS $p UTIA-B $4 070 $T Ústav teorie informace a automatizace AV ČR, v. v. i. 701 -1
$3 cav_un_auth*0218430 $a Kuneš $b Michal $i Zpracování obrazové informace $j Department of Image Processing $k ZOI $l ZOI $p UTIA-B $w Department of Image Processing $4 070 $T Ústav teorie informace a automatizace AV ČR, v. v. i. 701 -1
$3 cav_un_auth*0101213 $a Tichý $b Milan $i Zpracování signálů $j Department of Signal Processing $k ZS $l ZS $p UTIA-B $4 070 $T Ústav teorie informace a automatizace AV ČR, v. v. i. 856 $u http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf
Počet záznamů: 1