Software Phase Lock Loops Applied in Three-Phase PWM Rectifier

0365382 - ÚT 2012 RIV SK eng C - Konferenční příspěvek (zahraniční konf.)
Šimek, Petr - Škramlík, Jiří - Valouch, Viktor - Bejvl, Martin
Software Phase Lock Loops Applied in Three-Phase PWM Rectifier.
Electrical Drives and Power Electronics - EDPE 11. Košice: Technical University of Košice, 2011, s. 227-232. ISBN 978-80-553-0734-3.
[International Conference on Electrical Drives and Power Electronics - EDPE 11 /17./. Stará Lesná, The High Tatras (SK), 28.10.2011-30.10.2011]
Grant CEP: GA MPO(CZ) FR-TI1/330
Výzkumný záměr: CEZ:AV0Z20570509
Klíčová slova: phase lock loop * unsymmetrical voltage system * harmonics
Kód oboru RIV: JA - Elektronika a optoelektronika, elektrotechnika

Three SPLL (Software Phase Lock Loops)that differ by the method of the detection of symmetrical grid voltage sequences (positive and negative ones) are presented. Simulation and experimental results of these SPLL applied in a three-phase PWM rectifier connected to an unsymmetrical grid voltage system with harmonics are discussed, even under some disturbances and parameter changes of the grid. The function of the DSC (Delayed Signal Cancellation) based SPLL in PWM rectifier with fs = 1600 Hz was experimetally verified under different grid voltage disturbances with satisfactory results.
Trvalý link: http://hdl.handle.net/11104/0200635