Instruction Set Extensions for Multi-Threading in LEON3

0342262 - ÚTIA 2011 RIV US eng C - Konferenční příspěvek (zahraniční konf.)
Daněk, Martin - Kafka, Leoš - Kohout, Lukáš - Sýkora, Jaroslav
Instruction Set Extensions for Multi-Threading in LEON3.
Proceedings of the13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE, 2010, s. 237-242. ISBN 978-1-4244-6610-8.
[DDECS 2010 : 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Vídeň (AT), 14.04.2010-16.04.2010]
Grant CEP: GA MŠMT 7E08013
Grant ostatní: European Commission(BE) FP7-ICT-215216
Výzkumný záměr: CEZ:AV0Z10750506
Klíčová slova: multithreading * instruction set extensions * microthreading * LEON3 * SPARC * FPGA
Kód oboru RIV: JC - Počítačový hardware a software
http://library.utia.cas.cz/separaty/2010/ZS/danek-instruction set extensions for multi-threading in leon3.pdf

This paper describes instruction set extensions for a variant of multi-threading called micro-threading for the LEON3 SPARCv8 processor. We show an architecture of the developed processor and its key blocks - cache controller, register file, thread scheduler. The processor has been implemented in a Xilinx Virtex2Pro FPGA. The extensions are evaluated in terms of extra resources needed, and the overall performance of the developed processor is evaluated on a simple DSP computation typical for embedded systems.
Trvalý link: http://hdl.handle.net/11104/0185041