Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique

0346745 - ÚTIA 2011 RIV US eng C - Konferenční příspěvek (zahraniční konf.)
Heřmánek, Antonín - Kuneš, Michal - Tichý, Milan
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique.
Proceedings of the International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2010, s. 336-339. ISBN 978-0-7695-4179-2.
[20th International Conference on Field Programmable Logic and Applications. Milano (IT), 31.08.2010-02.09.2010]
Grant CEP: GA MŠMT 7H09005
Výzkumný záměr: CEZ:AV0Z10750506
Klíčová slova: FPGA * Clock Gating * Digital design * System on Chip * Multicore Embedded System * Power consumption
Kód oboru RIV: JA - Elektronika a optoelektronika, elektrotechnika
http://library.utia.cas.cz/separaty/2010/ZS/kunes-reducing power consumption of an embedded dsp platform through the clock-gating technique.pdf

The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the total power of the system. To achieve this, we reduce clock power consumption of the system by switching-off the clock signal for the parts of system that are not used. The system presented in this paper is based on the main processor, extended with several reconfigurable accelerators. These accelerators extend the processor capabilities by several vector operations and can be reprogrammed in run-time. Clock gating, in our design, is used to switch the accelerators off when not used. As the accelerators can represent a major part of the system size, switching them off can significantly reduce the power consumption. We also propose the method for estimation of the reduction of power consumption that can be achieved using the clock-gating technique.
Trvalý link: http://hdl.handle.net/11104/0187684