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UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs
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SYSNO ASEP 0380863 Document Type B - Monograph R&D Document Type Monograph Title UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs Author(s) Daněk, Martin (UTIA-B)
Kafka, Leoš (UTIA-B)
Kohout, Lukáš (UTIA-B) RID
Sýkora, Jaroslav (UTIA-B)
Bartosinski, Roman (UTIA-B)Number of authors 5 Issue data New York: Springer, 2013 ISBN 978-1-4614-2409-3 Series Circuits & Systems Number of pages 209 s. Publication form Print - P Language eng - English Country US - United States Keywords multi-threading ; micro-threading ; SPARC ; LEON3 ; hardware acceleration ; FPGA ; GRLIB Subject RIV JC - Computer Hardware ; Software R&D Projects 7E08013 GA MŠMT - Ministry of Education, Youth and Sports (MEYS) DOI https://doi.org/10.1007/978-1-4614-2410-9 Annotation This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. * Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; * Provides VHDL sources for the described processor; * Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; * Includes programming by example in the micro-threaded assembly language. Workplace Institute of Information Theory and Automation Contact Markéta Votavová, votavova@utia.cas.cz, Tel.: 266 052 201. Year of Publishing 2013
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