Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3

0357150 - ÚTIA 2011 RIV IT eng C - Konferenční příspěvek (zahraniční konf.)
Sýkora, Jaroslav - Kafka, Leoš - Daněk, Martin - Kohout, Lukáš
Analysis of Execution Efficiency in the Microthreaded Processor UTLEON3.
Architecture of Computing Systems - ARCS 2011. Berlin: Springer-Verlag Berlin Heidelberg, 2011 - (Berekovic, M.), s. 110-121. Lecture Notes in Computer Science - LNCS, 6566. ISBN 978-3-642-19136-7. ISSN 0302-9743.
[ARCS 2011. International Conference on Architecture of computing systems /24./. Camo (IT), 24.02.2011-25.02.2011]
Grant CEP: GA MŠMT 7E08013
Grant ostatní: European Commission(XE) FP7-ICT-215215
Výzkumný záměr: CEZ:AV0Z10750506
Klíčová slova: Processor architectures * Multi-threading
Kód oboru RIV: JC - Počítačový hardware a software

We analyse an impact of long-latency instructions, the family blocksize parameter, and the thread switch modifier on execution efficiency of families of threads in a single-core configuration of the UTLEON3 processor that implements the SVP microthreading model. The analysis is supported by code execution in an FPGA implementation of the processor. The conclusions drawn in this paper can be used to optimize code compilation for the microthreaded processor. As the compiler specifies the blocksize parameter for each family of threads individually, it can optimize the register file utilization of the processor.
Trvalý link: http://hdl.handle.net/11104/0195483